Data link layer device for a serial communication bus

ABSTRACT

According to the IEEE1394 bus protocol, priority is given to isochronous data packets. Data transfer is done in transfer cycles under the control of a cycle master. It depends on the allocated bandwidth for isochronous data how much transport capacity is available in a transfer cycle. To managed the mixed data transfer in one cycle it is specified that the bus nodes not having isochronous data to transfer need to wait with their transmission requests until the end of the isochronous data transfers in the cycle indicated with a sub-action gap. The invention aims to improve the efficiency of data transport for the case that none of the bus nodes need to transfer isochronous data. The data link layer devices according to the invention includes means for checking whether isochronous data is to be transferred and if not they switch over to a no cycle master state, in which the local cycle synchronization events are ignored. The nodes need not wait for a sub-action gap after a local cycle event before drawing asynchronous transmission requests.

The invention relates to the field of data communication over a serialcommunication bus. More particularly the invention relates to a datalink layer device for such a serial communication bus.

BACKGROUND

For quite a long time now the convergence of the product sectors ofconsumer electronics (HiFi, video, audio) on one side and personalcomputers on the other have been trumpeted under the catchwordmultimedia and have actually been propelled by many manufacturers fromboth camps. The merging of the two product sectors means that workconcerned with the subject of data exchange between the equipment of thedifferent product sectors or else between the equipment within oneproduct sector is becoming more and more significant. This is alsoapparent from the efforts for standardization with regard to thissubject, which are already well advanced. Specifically, the so-calledIEEE1394 serial bus already provides an internationally standardized andvery widely accepted bus for data exchange between terminals from bothproduct groups. The precise designation of the afore-mentioned standardis:

-   IEEE1394 standard for high performance serial bus, (IEEE) STD    1394/1995, IEEE New York, August 1996.

The invention that is to be described here is concerned with the busmanagement. This IEEE1394 bus provides the service of isochronous datatransfer as well as asynchronous data transfer. In this connectionisochronous data transfer means that data to be transmitted arrivesregularly at a data source the data also arriving with approximately thesame size each time. Examples of such data sources are video recordersor camcorders, DVD players, audio devices such as CD players or MP3players and the like. The asynchronous transfer mode is used for all theother data transfers including control commands and configurationmessages, which are not as critical as in the case of streaming video oraudio.

The specification of the IEEE1394 serial bus comprises a series ofcriteria, which are highly significant for products from the sector ofconsumer electronics:

-   -   Virtually freely selectable bus topology (e.g. chain, tree . . .        ) with up to 63 terminals,    -   Bit serial data transmission over a cable with 4 or 6 conductors        with the maximum distance of 4.5 meters between two pieces of        equipment,    -   Transmission rates of up to 400 MBit/s at present,    -   Terminals can be connected and disconnected during operation        (life insertion).

In order to produce an IEEE1394 interface it is necessary to implementtwo layers of the IEEE1394 standard using hardware: These are thephysical layer and data link layer which are known from theOSI/IEC-7-Layer reference model of data communication. The connection tothe bus is managed with the physical layer, while essential parts of thebus protocol are implemented in the data link layer. Since the galvanicseparation between the physical layer and the data link layer isprovided in the 1394 standard the implementation is generally effectedusing separate IC's.

In a given configuration of the 1394 bus the bus management assures thatthe bus is shared for transportation of isochronous data packets as wellas asynchronous data packets in a fair manner, this is basically done byintroducing a so-called cycle master in the network. It is a bus nodewith cycle master capability that will be assigned as cycle master. Thisbus node provides for time synchronisation for all bus nodes in thenetwork by means of transmitting in a regular intervals cycle startpackets. Every bus node has to resynchronise its time clock afterreception of a cycle start packet. To assure this synchronizationprocess, in each of the bus nodes there is a cycle timer running, thatgenerates with its own time clock local cycle synchronization events.After the local cycle synchronization event a bus node will wait for thereception of the cycle start packet before making own transmissionrequests. After reception of a cycle start packet a bus node will waitfor a short isochronous gap before generating a transmission request forisochronous data if any has become due. Each of the nodes having madeisochronous transmission requests will get access to the bus during thenominal cycle period. This is assured by an isochronous resource managerthat is also established in the 1394 standard. If the data transportcapacity of the 1394 bus has not been seized by the isochronous manager,all the other nodes having made asynchronous transmission requests canaccess to the bus after elapse of a certain amount of time calledsub-action gap. The rest of the cycle period is, therefore, dedicatedfor asynchronous transmissions.

The shortly explained bus management procedure where the isochronousdata transport capacity is guaranteed and the remaining data transportcapacity is reserved for asynchronous transmissions has the followingdrawback: In case of the use of the IEEE1394 bus for serialcommunication between devices that do not need to transfer isochronousdata, the bus management with the cycle master and dedicated cycleperiods is not the most efficient one. Each bus node has to wait for thereception of the cycle start packet after each local cyclesynchronization event and also it has to wait for the sub-action gabbefore it can request asynchronous transmission. This is somehow a wasteof time namely the transmission time for the cycle start packet as wellas the waiting time for the sub-action gap. During this time in each ofthe cycle periods no data transport can take place.

INVENTION

It is an object of the invention to overcome the above-explaineddrawback of the bus management in an IEEE1394 bus based on a cyclemaster in cycle periods. In other words it is the object of theinvention to disclose an improved bus management with a more efficientuse of the data transport capacity of the serial bus.

These and other objects are achieved with the measures listed inindependent claims 1 and 3. According to claim 1 the solution consistsin the provision of configuration means in a data link layer device fora serial communication bus with which the generation or submission of acycle start packet in succession to a local cycle synchronization eventare disabled in response to a predetermined condition in order tosupport a no cycle master transfer mode.

In the case of claim 1 the data link layer device is itself the cyclemaster in the network but before acting as a cycle master this data linklayer device checks whether an isochronous resource manager has actuallyallocated band-widths for the isochronous data transfer. If this is notthe case, the data link layer device according to the invention willswitch over into a no cycle master state and will not produce the cyclestart packets in order to improve the efficiency of data transport.

Independent claim 3 discloses another solution according to theinvention from the point of view of a data link layer device beingintegrated in a bus node that either does not have cycle mastercapability or acts as cycle slave i.e. it did not try or succeed tobecome the cycle master in the bus. For such a data link layer device itis advantageous to implement means for checking whether a cycle masterexists in the network and if not activating configuration means thatswitch over to a no cycle master mode. In this mode, the generation ofasynchronous transmission requests is enabled without waiting for acycle start packet and an asynchronous data transfer raster is enabled.

With both implementations, it is possible to increase data transportcapacity in the network.

Further improvements of the data link layer device as defined in claim 3are possible by virtue of the measures evinced in the dependent claims 4and 5. There are two possibilities how to check whether a cycle masterexists in the network. One is based on the evaluation of theself-identification packets from all the nodes in the network stored inthe internal memory of the data link layer device. After a bus reseteach bus node, i.e. each data link layer device collects all theself-identification packets transmitted from the bus nodes in the busreset phase and stores them in its internal memory. According to theIEEE1394 standard the self-identification packet has the format thatthere is an entry existing that indicates that the corresponding node isa contender for an isochronous resource manager. If in none of theself-identification packets this entry is set, it is clear that nobodyon the net would like to transfer isochronous data packets and,therefore, each data link layer device can switch over to the no cyclemaster state.

An alternative solution for checking whether a cycle master exists inthe network consists in the provision of a first counter counting clockpulses of a reference clock, the counter generating a cyclesynchronisation event each time after a predetermined counting intervaland a second counter that is incremented each time that no cycle startpacket has been received in succession to a cycle synchronization eventand if the second counter reaches a predetermined value the switchingover to the no cycle master trahsfer mode is done.

DRAWINGS

Exemplary embodiments of the invention are illustrated in the drawingsand are explained in more detail in the following description.

In the figures:

FIG. 1 shows an example of an IEEE1394 bus configuration with a personalcomputer, XDSL modem, printer and digital still camera;

FIG. 2 shows a simple block diagram for an IEEE1394 interface;

FIG. 3 shows the IEEE1394 serial bus protocol stack;

FIG. 4 shows the cycle structure according to the IEEE1394 bus protocol;

FIG. 5 shows a simplified diagram for illustrating the cycle mastertransfer mode;

FIG. 6 shows the structure of the no cycle master transfer modeaccording to the invention;

FIG. 7 shows a block diagram of a data link layer device;

FIG. 8 shows the format of an IEEE1394 self identification packet;

FIG. 9 shows a first state diagram for a data link layer device beingconfigured as a cycle slave; and

FIG. 10 shows a second state diagram for a data link layer device beingconfigured as a cycle slave.

In FIG. 1 reference number 10 denotes a personal computer. To thepersonal computer 10 is connected via 1394 cables an XDSL modem 11, aprinter 12 and a digital still camera 13. The XDSL modem 11 is connectedto the telephone line and over this line has access to the Internet. Thepersonal computer 10 needs to be equipped with at least a 3 port 1394physical layer IC in order to be able to handle all connections to theperipheral devices 11 to 13. The bus configuration such as shown in FIG.1 is characterized by the fact that none of the peripheral devices 11 to12 have the capability of transmitting or receiving isochronous datapackets. There is no streaming audio or video possible with a printer, adigital still camera or an XDSL modem according to this embodiment. Thepersonal computer 10 can have the capability to receive and sendisochronous data packets but in this configuration it will not make useof this capability because none of the peripheral devices can managethese isochronous data packets. All the traffic on the 1394 bus willtherefore relate to asynchronous transmissions.

FIG. 2 shows the principle structure of an IEEE1394 interface. Two ofthe communication layers according to the OSI/ISO reference model ofdata communication need to be implemented by hardware. These are thephysical layer and the data link layer. According to the IEEE1394standard a galvanic insulation between the physical layer circuit andthe data link layer circuit may be implemented. Therefore, in FIG. 2 twoseparate IC's are depicted for the data link layer and the physicallayer. Reference number 20 denotes the IC for the physical layer andreference number 30 denotes the IC for the data link layer. The physicallayer IC is connected to the 1394 bus lines DTx, StrbTX, DRx, andStrbRx. Also shown are the connection lines between the physical layerIC 20 and the data link layer IC 30. There are up to 8 lines dedicatedto the data bit transfer, two lines are dedicated to the control betweenboth IC's and there is a link request line LReq from the link IC toPHY-IC. Depicted is also the connection of the link IC to an externalmicrocontroller without listing the details of this connection. Alsoshown is a clock generator 14 that delivers a quartz stabilized clock of49.512 MHz to the PHY-IC 20. This clock signal is also fed to a divideby two circuit 15 that reduces the clock frequency to the half of theclock generator 14. The reduced clock signal at 24.576 MHz is deliveredto the link IC 30. This clock is used to increment a 32-bit cycle timerregister in the link IC 30 which will be explained later on in furtherdetail. In another embodiment of the invention the divide by two circuitis integrated in the link IC.

FIG. 3 shows the bus protocol stack such as shown in the IEEE1394 busstandard. Separately shown is on the right side the physical layer 20,the data link layer 30 and the transaction layer 50. All of the upperlayers are not specified in the IEEE1394 bus standard. On the left sideof FIG. 3 are shown the serial bus management software tools like a busmanager 41, an isochronous resource manager 42 and a node controller 43.These tools are realized mostly by means of software running on amicrocontroller of the respective 1394 bus node. The same applies to thetransaction layer implementation. Only the physical layer and the datalink layer are implemented by means of hardware. Important parts for thephysical layer 20 are the following components. An arbitration logic 21,a connector/media logic 22, a data re-synchronization logic 23, a businitialisation logic 24, an encoding/decoding logic 25 that serves fordata strobe encoding/decoding and a bus signal level generation anddecoding logic 26. For the complete details to the different logic andto the physical layer functionality it is referred to the IEEE1394 busstandard itself.

More important for the present invention is the implementation of thedata link layer protocol 30. FIG. 3 depicts three separate componentssuch as cycle control logic 31, packet receiver 23 and packettransmitter 32. The structure of the data link layer implementation willbe explained in greater detail hereinafter. However, to all the featuresof the link layer not being important to the present invention it isalso referred to the IEEE1394 bus standard. For exchanging informationwith one of the other layers as well as with the serial bus managementitem, a number of requests, configuration, indication and registeraccess messages are depicted in FIG. 3, that will not be explained indetail here. These are standardised messages and it is also referred tothe 1394 bus standard in order to disclose these messages. Thefunctionality of the transaction layer 50 is also disclosed in the 1394bus standard. There is no modification required for the implementationof the present invention here.

The serial bus protocols also include serial bus management, whichprovides the basic control functions and standard control and statusregisters (CSR) needed to control nodes or to manage bus resources. Thebus manager component is only active at a single node exercisingmanagement responsibilities over the entire bus. At the nodes beingmanaged (all those that are not the bus manager) the serial busmanagement consists solely of the node controller component. Anadditional component, the isochronous resource manager 42, centralisesthe services needed to allocate bandwidth and other isochronousresources. The isochronous resource manager 42, for example, isimplemented by software means where a number of special purposeregisters are defined for the isochronous resource manager. For exampleone of these registers corresponds to the information how muchisochronous bandwidth is currently allocated for the network. Theseregisters can be accessed from the data link layer. This will beutilized for the purpose of the implementation of the invention asexplained later on.

As already mentioned in the consistory clause of the application, theIEEE1394 bus standard provides for data transfer in cycle periods. Sucha cycle period is shown in FIG. 4. The basic transfer mode is called amanaged bus where a cycle master maintains a common clock over thenetwork. In the cable environment, the highest priority node is a routeand the cycle master must be the route. The cycle master tries totransmit a cycle start packet at specific intervals for example each 125μs. If the transfer is in progress when the cycle synchronization eventoccurs, then the cycle start packet will be delayed, causing significantjitter in the start time of the transfer. Since this jitter isfrequently unacceptable, the amount of time that the cycle start packetwas delayed is encoded within the packet as a transaction layer quadletwrite request broadcast to each node's cycle timer register. All theother nodes can synchronize their cycle timer register entries to thisvalue. The nodes have a 32-bit cycle timer register. The low order 12bits of the register are a modulo 3072 count, which increments once each24.576 MHz clock period. The next 13 higher order bits are a count of 8kHz cycles and the highest order 7-bits count seconds. A localsynchronization event is generated in each of the nodes when the loworder 12-bits of the cycle timer register wrap from 3071 to zero. Thisis equivalent to a cycle synchronization event in intervals of 125 μs.All nodes not being the cycle master respond to the occurrence of alocal cycle synchronization event by waiting for a cycle start packetbefore making another transmission request. The nodes are waiting atleast for the time period of a sub-action gap after a data transmissionin progress when the cycle sync event occurred. After the reception ofthe cycle start packet they only have to wait for a shorter isochronousgap before setting their own isochronous transmission requests. All busnodes not having isochronous data to transmit wait for anothersub-action gap after the last isochronous data packet before they drawtheir own asynchronous transmission requests.

The data transfer under the cycle master control is also depicted inFIG. 5 in simplified manner. On top of FIG. 5 is shown the local cyclesync event. The bus node having cycle master functionality waits for theend of the data transfer in progress and then generates and submits thecycle start packet over the bus. During all the time from the localcycle sync event until the end of the transmission of the cycle startpacket all asynchronous transmission requests as well as isochronoustransmission requests are forbidden. Asynchronous transmission requestsremain forbidden in the following time period right after the receptionof the cycle start packet in order to guarantee the isochronous datatransmission first. This period ends with the occurrence of a sub-actiongap on the bus behind the isochronous bus traffic. Shown in the thirdand fourth line of FIG. 5.

With the invention a new transfer mode will be introduced with the maincharacteristic that no cycle master is present on the bus. This transfermode will be entered after having firstly set up the normal transfermode, where the timer registers had been synchronized. Then the no cyclemaster transfer mode will be entered after having detected that twiceafter the occurrence of the local cycle sync event no cycle start packethas been received. Line 3 of FIG. 6 shows that in the first cycle periodafter a local cycle sync event, the ordering of asynchronoustransmission requests are forbidden. Only after not having received acycle start packet behind the second local cycle sync event theasynchronous transmission requests are enabled and the no cycle masterstate is detected. Upon switching over to the no cycle master state thedata link layer device is reconfigured to the no cycle master transfermode in which subsequent local cycle sync events are ignored andasynchronous transmission requests are allowed during the whole cycleperiod.

In FIG. 7 the principle structure of the data link layer device isshown. Identical reference numbers with one of the foregoing drawingsdenote the same components as previously claimed. The structure of thisdata link layer device is based on the structure of the TSB12LV01A datalink layer IC from Texas Instruments. For the purpose of the disclosureof the invention it is therefore also referred to the data sheet of thisIC. The physical layer interface 35 interfaces on one hand to thetransmitter and receiver components 32 and 33 and on the other hand italso interfaces to the physical layer chip and conforms to the PHY-Linkinterface specification described in Annex J of the IEEE1394 busstandard. The transmitter 32 retrieves data from the internal memory 37and creates correctly formatted serial bus packets to be transmittedthrough the PHY interface 35.

The receiver takes incoming data from the PHY interface 35 anddetermines if the incoming data is addressed to this node. If theincoming packet is addressed to this node, the CRC of the packet headeris checked in CRC calculation unit 34. If the header CRC is good, theheader will be stored in the internal memory 37. The internal memory 37is organized in two transmit FIFO and one receive FIFO. Each of theseFIFO is a quadlet wide.

The cycle timer 31 a is a 32-bit register. The cycle timer registerconsists of three fields, cycle offset, cycle count and seconds count.As explained before the low order 12-bits of the timer are a module 3072counter, which increment once every 24.576 MHz clock period, therebywrapping after exactly 125 μs. The next 13 higher order bits are a countof 8,000 Hz or 125 μs cycles and the highest 7-bits count seconds.

The cycle monitor 31 b not only generates a local cycle sync event italso monitors the reception or transmission of cycle start packets.Hence it re-synchronizes the cycle timer with the entry of the receivedcycle start packet. The cycle monitor detects and counts missing cyclestart packets after a local cycle sync event and makes the switch overto the no cycle master state as explained above.

The configuration registers 38 control the operation of the data linklayer device in the well-known manner of the CSR (control and statusregister) architecture. The host bus interface 36 allows an easyconnection to a host processor.

In connection with FIG. 6 a first embodiment of how the data link layerdevice can be switched over to the no cycle master transfer mode hasbeen explained. It is possible to do this switch over process in analternative manner. This alternative solution is based on the analysisin the data link layer device of all the self identification packetscollected from all bus nodes after a bus reset and stored in itsinternal memory. The structure of a self-identification packet is shownin FIG. 8. The first two bits correspond to the self-identificationpacket identifier. The following 6 bits relate to the physical nodeidentifier of the sender of this packet. The L bit is set if an activelink and transaction layer is present in the sender of this packet. Thefollowing 6 bits correspond to a gap count value. The 2 bits sp informabout the speed capabilities of the bus node sending this packet. Thetwo bits dil inform about a worse case repeater data delay. The c bit isset if the sending node is a contender for a bus or isochronous resourcemanager. It is this bit which needs to be analysed in order to determinewhether the no cycle master mode can be entered or not. The pwr bitsinform about the power consumption and source characteristics of thenode. The bits for the fields p0, p1, p2 inform about the port status ofthe sending node. The i bit is set if the sending node has initiated thecurrent bus reset. The m bit indicates that another self-identificationpacket will follow for this node or not. The second quadlet in theself-identification packet #0 is a logical inverse of the first quadletfor error checking purposes. By evaluating whether in any one of thecollected self-identification packets the c bit is set the data linklayer cycle monitor 31 b can find out if either isochronous traffic willoccur or not. In case that none of the self identification packets haveset the c bit, it is immediately clear, that there is no isochronousresource manager in the network and therefore that no isochronousservice can be provided. In consequence an immediate switch over to theno cycle master state can be made. With this solution the switch over tothe no cycle master state can be made faster in comparison to thepreviously explained solution according to FIG. 6.

The two alternative solutions are also disclosed in the following FIGS.9 and 10. FIG. 9 shows the state diagram for the first disclosedsolution. In the cycle master state of the data link layer device eachlocal cycle sync event followed by a cycle start packet detection resetsa counter to the value zero. After detection of a local cycle sync eventwithout following reception of a cycle start packet the counter will beincremented. The data link layer device switches over to the no cyclemaster state if the counter value has reached a predetermined value n.The no cycle master state will be left if a cycle start packet has beendetected and the data link layer device goes back to the cycle masterstate.

In the state diagram for the alternative solution according to FIG. 10it will be switched over to the no cycle master state if an evaluationof all the self identification packets has disclosed that none of theconnected bus nodes contended for isochronous resource manager asdescribed in connection with FIG. 8. Again, the no cycle master statewill be left upon detection of a cycle start packet, then going back tothe cycle master state.

The two alternatively disclosed solutions are appropriate for bus nodesthat cannot act as a cycle master. For the situation shown in FIG. 1this would be the case for all the peripheral devices 11, 12 and 13. Thepersonal computer 10 however would have cycle master capability as wellas isochronous resource capability. The data link layer device locatedin the personal computer 10 can however directly enter the no cyclemaster state if it was configured to be the root, the isochronousresource manager and the cycle master after the self configurationphase. It simply needs to draw a request to the isochronous resourcemanager requesting the information about the isochronous bandwidthallocation. This can be made by the cycle monitor 31 b via the hostinterface 36 in the well-known manner. The host processor has a softwareregister for the information about the allocated isochronous bandwidth.This will be read out via the host interface 36 and the cycle monitor 31b can switch over to the no cycle master state if no isochronousbandwidth had been allocated.

1. Data link layer device for a serial communication bus, in particularIEEE1394 bus, comprising an interface to a physical layer unit and aninterface to at least one host processor supporting the higher layers ofthe OSI/ISO data communication reference model, wherein, the data linklayer device further comprises means for checking whether a cycle mastercapable of transmitting a cycle start packet determining minimum starttimes for isochronous and asynchronous data transmissions over theserial communication bus exists in the network and if not activatingconfiguration means that enable the generation of asynchronoustransmission requests without waiting for a cycle start packet and anisochronous data transfer in order to support a no cycle master transfermode.
 2. Data link layer device according to claim 3 wherein the meansfor checking whether a cycle master exists in the network comprise amemory storing the self-identification packets from all the nodes in thenetwork and evaluating means for checking whether in one of theself-identification packets an entry is found that indicated that thecorresponding node is contender for an isochronous resource manager. 3.Data link layer device according to claim 3, wherein the means forchecking whether a cycle master exists in the network comprise a firstcounter counting clock pulses of a reference clock, the countergenerating a cycle synchronization event each time after a predeterminedcounting interval, and comprising a second counter that is incrementedeach time that no cycle start packet has been received in succession toa cycle synchronization event, thereby activating said configurationmeans if the second counter reaches a predetermined value.
 4. Data linklayer device according to claim 3 wherein the means for checking whethera cycle master exists in the network comprise a memory storing theself-identification packets from all the nodes in the network andevaluating means for checking whether in one of the self-identificationpackets an entry is found that indicated that the corresponding node iscontender for an isochronous resource manager.
 5. Data link layer deviceaccording to claim 3, wherein the means for checking whether a cyclemaster exists in the network comprise a first counter counting clockpulses of a reference clock, the counter generating a cyclesynchronization event each time after a predetermined counting interval,and comprising a second counter that is incremented each time that nocycle start packet has been received in succession to a cyclesynchronization event, thereby activating said configuration means ifthe second counter reaches a predetermined value.